This disclosure relates to alignment using latent images.
In order to successively pattern a substrate using lithography or other fabrication processes, the features in each pattern must generally be properly aligned relative to the features of both prior and successive patterns. Misalignment between features in different patterns is generally termed “overlay error” and can be caused, e.g., by reticle misalignment, reticle-to-wafer misalignment, uncompensated rotation of the wafer and/or reticle, uncompensated physical changes in the wafer, and other discrepancies.
Many systems for patterning substrates include one or more alignment devices to minimize overlay error. For example, a patterning system can include a wafer pre-aligner that receives a semiconductor wafer and coarsely aligns the wafer (e.g., to within +/−10 μm or so) such that alignment marks on the wafer are within the capture range of finer alignment devices. Examples of such finer alignment devices include wafer alignment systems that compare the intended and actual location of the wafer after pre-alignment and correct wafer misalignment down to fractions of micrometers. The accuracy of such systems is typically below 300 nm, but some commercial systems can achieve accuracies below 50 nm.
Like reference symbols in the various drawings indicate like elements.